1. Field
This disclosure relates generally to memory power management and, more specifically, to synchronized command throttling for multi-channel duty-cycle based memory power management.
2. Related Art
Power management has been implemented as a feature of some electrical devices (e.g., copiers, computer systems, and computer system peripherals, such as monitors and printers) to turn-off device power or switch the device to a low-power state when the device is inactive. In computing, personal computer (PC) power management has been built around the advanced configuration and power interface (ACPI) standard. The ACPI standard provides for unified operating system (OS) device configuration and power management and defines platform independent interfaces for hardware discovery, configuration, power management, and monitoring.
In general, computer system power management is desirable to: reduce overall energy consumption; prolong battery life for portable and embedded systems; reduce cooling requirements; reduce noise; and reduce operating costs associated with energy and cooling. Reduced power consumption leads to reduced heat dissipation (which increases system stability) and less energy use (which saves money and reduces environmental impact). Power management for processors can be implemented over an entire processor or in specific processor areas. For example, dynamic voltage scaling and dynamic frequency scaling may be employed to reduce a processor core voltage and clock rate, respectively, to lower processor power consumption, albeit at lower processor performance.
In addition to lower power consumption, power management techniques are also used to dynamically allocate power usage to various components within a system while staying with an overall system power envelope. For example, if dynamic random access memory (DRAM) power can be temporarily limited to some value lower that its normal maximum, the saved power can then be allocated to processor cores to increase voltage and clock rate, and, as a result, performance can be increased during periods of high processor utilization. Conversely, during periods of relatively low processor core utilization and high DRAM utilization, core power can be temporarily limited and saved power can be allocated to DRAM to allow for additional memory bandwidth.
Advances in semiconductor process technology have allowed microprocessor designers to increasingly locate more processor cores on each integrated circuit (chip), while staying within a given power envelope. In addition to processor cores, other functions have been incorporated in various chips to provide system-on-a-chip (SOC) architectures. However, process scaling due to advances in semiconductor process technology has not been uniform across all device types. For example, DRAM has not scaled (in capacity or speed) as quickly as processors, due to advances in semiconductor process technology. As a result, DRAM has generally become the single largest power consumer in fully-configured enterprise class computing systems. In general, as the number of processor cores is increased, the demand for additional memory capacity and memory bandwidth increases. However, as noted above, increasing DRAM increases the need for additional system power delivery and power dissipation capability.